FIG. 1 shows an embodiment of a computing system. The exemplary computing system of FIG. 1 includes: 1) one or more processors 101; 2) a memory control hub (MCH) 102; 3) a system memory 103 (of which different types exist such as RDRAM, SDRAM, EDO RAM, etc,); 4) a cache 104; 5) an I/O control hub (ICH) 105; 6) a graphics controller 106; 7) a display/screen 107 (of which different types exist such as Cathode Ray Tube (CRT), TFT, LCD, etc.). The one or more processors 101 execute instructions in order to perform whatever software routines the computing system implements. The instructions frequently involve some sort of operation performed upon data. Both data and instructions are stored in system memory 103 and cache 104. Cache 104 is typically designed to have shorter latency times than system memory 103. For example, cache 104 might be integrated onto the same silicon chip(s) as the processor(s) and/or constructed with faster SRAM cells whilst system memory 103 might be constructed with slower DRAM cells.
By tending to store more frequently used instructions and data in the cache 104 as opposed to the system memory 103, the overall performance efficiency of the computing system improves. System memory 103 is deliberately made available to other components within the computing system. For example, the data received from various interfaces to the computing system (e.g., keyboard and mouse, printer port, LAN port, modem port, etc.) or retrieved from an internal storage element of the computing system (e.g., hard disk drive) are often temporarily queued into system memory 103 prior to their being operated upon by the one or more processor(s) 101 in the implementation of a software program.
Similarly, data that a software program determines should be sent from the computing system to an outside entity through one of the computing system interfaces, or stored into an internal storage element, is often temporarily queued in system memory 103 prior to its being transmitted or stored. The ICH 105 is responsible for ensuring that such data is properly passed between the system memory 103 and its appropriate corresponding computing system interface (and internal storage device if the computing system is so designed). The MCH 102 is responsible for managing the various contending requests for system memory 103 access amongst the processor(s) 101, interfaces and internal storage elements that may proximately arise in time with respect to one another.
Another computing system component that the MCH 102 may have to deal with (because it requests access to the system memory 103) is the graphics processor 106. The graphics processor 106 can be viewed as a co-processor that “takes on” the responsibility of performing sophisticated instructions associated with the presentation of complex visual images on the computing system's display 107. By removing such responsibility from processor(s) 101, the performance efficiency of the processor(s) is improved. The graphics processor 106 is designed to execute display image specific instructions so that display image specific software routines can be executed.
That is, the display image specific software routines are typically written in a language or format that can be broken down into instructions that the graphics processor can execute. Examples of such display image specific software languages/formats include OpenGL and D3D. In a typical case, a software driver beneath the main operating system (OS) (noting that the main OS is substantially executed on the processor(s) 101) is responsible for ensuring that instructions derived from software written in an display image specific software language/format (e.g., OpenGL or D3D) are forwarded to the graphics processor 106.
It should be noted that various other computing system architectures that include graphics processors yet depart from the particular architecture observed in FIG. 1 are possible. As such, the following discussion should not be considered as being automatically limited to the architecture of FIG. 1.